1. Field of the Invention
The present invention relates to a data processing device, and more particularly, to a data processing device having a data processing unit that can simultaneously receive double precision data as an input.
2. Description of the Background Art
A data processing unit of a conventional 16-bit DSP (Digital Signal Processor) has a circuit as illustrated by the functional block diagram shown in FIG. 8, in order to precisely and efficiently execute a product-sum operation for 16-bit signed data. The data processing unit includes a multiplier 1001 multiplying 16-bit signed data with each other at every cycle; an adder-subtractor 1002 dedicated to the product-sum operation and capable of handling 40-bit data; an adder-subtractor 1003 dedicated to addition/subtraction and capable of handling 40-bit data; and accumulators 1004 and 1005 each storing 40-bit data.
Adder-subtractors 1002 and 1003, and accumulators 1004 and 1005 are designed to handle 40-bit data for securing sufficient process precision in the product-sum operation. The multiplication result of 16-bit data will be in a dynamic range of 32 bits, and the result obtained by accumulating the multiplication result will be in an even larger dynamic range.
The function of reading one data and one coefficient from a memory (not shown) per cycle is realized by a configuration including a plurality of independent buses such as PB (Program Bus), CB, DB and EB. The buses CB and DB are connected to the memory. The memory here may be a two-port memory or a memory to which two accesses can be executed in one cycle. Thus, the use of the buses CB and DB enables simultaneous reading of two pieces of data.
In the data processing unit of such a DSP, adder-subtractors 1002 and 1003 can handle 40-bit data, so that it is easy to perform addition/subtraction of double precision data (32-bit data) stored in the accumulators with each other. However, when the 32-bit data stored in the memory is used as an operand, a transfer path between the memory and adder-subtractors 1002 and 1003 is only for 16 bits. Thus, desired data stored in the memory cannot be supplied to adder-subtractors 1002 and 1003 in one cycle. Therefore, adder-subtractors 1002 and 1003 capable of handling 40 bits cannot be efficiently operated.
The present invention was made to solve the above problem, and an object of the present invention is to provide a data processing device capable of efficiently operating an adder/subtractor.
A data processing device according to an aspect of the present invention includes a memory system capable of a plurality of simultaneous accesses; a plurality of address generators connected to the memory system, each of which generating an address for accessing the memory system; an addressing register connected to the plurality of address generators and having a plurality of address registers; a data processing unit connected to the memory system and providing an operation process to data read from the memory system; and a control unit connected to the addressing register, the plurality of address generators and the data processing unit, and controlling operations of the plurality of address generators and the data processing unit; the plurality of address generators being capable of generating addresses from a common value in one address register of the plurality of address registers to simultaneously read data designated by the generated addresses from the memory system.
A plurality of addresses are generated by the plurality of address generators, and the same memory system is accessed. This allows reading and writing of double precision bit data in one cycle. Further, the addresses are generated based on the same addressing register. This allows reduction of the number of registers.
Preferably, a part or all of the plurality of address generators each include a next address calculating unit connected to the addressing register and performing calculation of a next address based on a value held in the addressing register; and an updating unit connected to the addressing register and to the next address calculating unit, and updating the value held in the addressing register based on a calculation result of the next address calculating unit.
Provision of the next address calculating unit and the updating unit allows simultaneous execution of address updating and data operation. As a result, the number of processing cycles can be reduced.
More preferably, the addressing register includes a selecting register designating any one of the plurality of address registers. The control unit directly designates by an instruction field an address register to be referred by an address generator of the plurality of address generators during register indirect addressing, and indirectly designates by the instruction field an address register to be referred by another address register, based on a value stored in the selecting register.
By designating the operation information of an address generator using the register indirect addressing, the instruction field can be saved.
More preferably, each of the plurality of address generators selects an updating method in accordance with a predetermined precedence when the plurality of address generators have different methods of updating addresses.
For example, the operation contents that were directly designated in the instruction field can have a precedence. This eliminates the needs for rewriting of the contents of a mode register.
More preferably, the data processing unit includes an adder-subtractor having first and second input ports having a bit width of at least (N+M) bits, N being a bit size of a memory access port accessed by the register indirect addressing and M being a bit size of another memory access port accessed by the register indirect addressing, and receiving data of (N+M) bits read from the one memory access port and the another memory access port and connected together at at least one of the first and second input ports.
By combining the data read from the two memory access ports to configure a numeric value, the number of processing cycles for addition/subtraction with double precision can be reduced.
More preferably, data processing unit further includes an accumulator capable of storing data having a bit length of at least (N+M) bits. The control unit stores into the accumulator the data of (N+M) bits read from the one memory access port and the another memory access port and connected together.
More preferably, a part or all of the plurality of address generators each includes a first register holding a start address, and a second register holding an end address. The control unit performs modulo addressing based on values held in the first and second registers.
Further preferably, a part or all of said plurality of address generators each include at least one reference register holding a reference value and is capable of selectively outputting, as an address, a first value stored in one of the plurality of addressing registers as it is and a second value, which is an operation result of an operation on the first value and a value stored in at least one reference register.